PIC24FJ64GB106 Data Sheet
http://www.microchip.com/stellent/images/mchpsiteimages/dwnfolder.gifPIC24FJ256GB110 Family Data Sheet (4/9/2008)CPU
- Up to 16 MIPS performance
- 16 x 16 Hardware Multiply, Single Cycle Execution
- 12-bit x 16-bit Hardware Divider
- C Compiler Optimized Instruction Set
nanoWatt Power Managed Modes
- Run, Idle and Sleep modes
- Multiple, Switchable Clock Modes for Optimum Performance and Power Management
- Run mode: 1 mA/MIPS, 2.0V Typical
- Sleep mode Current Down to 100 nA Typical
- Standby Current with 32 kHz Oscillator:2.5 uA,2.0V typical
Flash Program Memory
- Self-Reprogrammable under Software Control
- 10,000 erase/write cycles
- 20 year data retention
- EEprom emulation capable
System
- Internal oscillator support - 31 kHz to 8 MHz, up to 32 MHz with 4X PLL
- On-chip LDO Voltage Regulator
- JTAG Boundary Scan and Flash Memory Program Support
- Fail-Safe Clock Monitor – allows safe shutdown if clock fails
- Watchdog Timer with separate RC oscillator
Analog Features
- 10-bit ADC, 16 channels, 500k samples per second
- Three Analog comparators
Universal Serial Bus Features
- USB v2.0 On-the-Go compliant
- Dual role capable, can act as either Host or Device
- Low speed(1.5Mb/s) and full speed(12 Mb/s) operation in host mode
- Full speed USB operaton in Device mode
- Supports 32 endpoints
- On-chip USB transceiver
Peripherals
- CTMU supports Capacitive Touch applications
- Perpheral Pin Select allows I/O remapping of many peripherals in real time
- 4xUART Modules with LIN and IrDA support, 4 Deep FIFO
- 3xSPI ™ Modules with 8 Deep FIFO
- 3xI2C™ Modules with Master and Slave Modes
- Five 16-bit Timer Modules
- Up to 9 Input Capture and 5 Output Compare/PWM with dedicated time base
- Hardware RTCC, Real-Time Clock Calendar with Alarms
- PMP, Parallel Master Port, with 16 Address Lines, and 8/16-bit Data
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