标题: PIC24HJ32GP204 Data Sheet [打印本页] 作者: enroo_ma 时间: 2009-7-25 11:29 标题: PIC24HJ32GP204 Data Sheet PIC24HJ32GP202/204 and PIC24HJ16GP304 Data Sheet (6/24/2009)
Linear data memory addressing up to 64 Kbytes
71 base instructions, mostly 1 word/1 cycle
Sixteen 16-bit General Purpose Registers
Flexible and powerful addressing modes
Software stack
16 x 16 multiply operations
32/16 and 16/16 divide operations
Up to ±16-bit shifts for up to 40-bit data
Interrupt Controller:
5-cycle latency
118 interrupt vectors
Up to 21 available interrupt sources
Up to 3 external interrupts
7 programmable priority levels
4 processor exceptions
On-Chip Flash and SRAM:
Flash program memory (up to 32 Kbytes)
Data SRAM (2 Kbytes)
Boot and General Security for Program Flash
Digital I/O:
Peripheral Pin Select Functionality
Up to 35 programmable digital I/O pins
Wake-up/Interrupt-on-Change for up to 21 pins
Output pins can drive from 3.0V to 3.6V
Up to 5V output with open drain configuration
All digital input pins are 5V tolerant
4 mA sink on all I/O pins
System Management:
Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
Power-up Timer
Oscillator Start-up Timer/Stabilizer
Watchdog Timer with its own RC oscillator
Fail-Safe Clock Monitor
Reset by multiple sources
Power Management:
On-chip 2.5V voltage regulator
Switch between clock sources in real time
Idle, Sleep and Doze modes with fast wake-up
Timers/Capture/Compare:
Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- 1 timer runs as Real-Time Clock with external
32.768 kHz oscillator
- Programmable prescaler
Input Capture (up to 4 channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
Output Compare (up to 2 channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM Mode
Communication Modules:
4-wire SPI
- Framing supports I/O interface to simple codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and sampling modes
I2C™
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
UART
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
Analog-to-Digital Converters (ADCs):
10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- 2 and 4 simultaneous samples (10-bit ADC)
- Up to 10 input channels with auto-scanning
- Conversion start can be manual or synchronized with 1 of 4 trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
CMOS Flash Technology:
Low-power, high-speed Flash technology
Fully static design
3.3V (±10%) operating voltage
Industrial and extended temperature
Low-power consumption
Packaging:
28-pin SDIP/SOIC/QFN-S
44-pin QFN/TQFP
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