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PIC18F6410 Data Sheet

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发表于 2009-8-1 18:25:17 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
  PIC18F6310/6410/8310/8410 Data Sheet (10/20/2010)

Power-Managed Modes:
ï Run: CPU on, Peripherals on
ï Idle: CPU off, Peripherals on
ï Sleep: CPU off, Peripherals off
ï Idle mode Currents Down to 5.8 μA Typical
ï Sleep mode Currents Down to 0.1 μA Typical
ï Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
ï Watchdog Timer: 2.1 μA
ï Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
ï Four Crystal modes:
- LP: up to 200 kHz
- XT: up to 4 MHz
- HS: up to 40 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
ï 4x Phase Lock Loop (available for crystal and
internal oscillators)
ï Two External RC modes, up to 4 MHz
ï Two External Clock modes, up to 40 MHz
ï Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz to
8MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
ï Secondary Oscillator using Timer1 @ 32 kHz
ï Fail-Safe Clock Monitor:
- Allows for safe shut down of device if primary
or secondary clock fails
External Memory Interface
(PIC18F8310/8410 Devices only):
ï Address Capability of up to 2 Mbytes
ï 16-Bit/8-Bit Interface
Peripheral Highlights:
ï High-Current Sink/Source 25 mA/25 mA
ï Four External Interrupts
ï Four Input Change Interrupts
ï Four 8-Bit/16-Bit Timer/Counter modules
ï Up to 3 Capture/Compare/PWM (CCP) modules
ï Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I
2Cô
Master and Slave modes
ï Addressable USART module:
- Supports RS-485 and RS-232
ï Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Detect
ï 10-Bit, up to 12-Channel Analog-to-Digital (A/D)
Converter module:
- Auto-acquisition capability
- Conversion available during Sleep
ï Dual Analog Comparators with Input Multiplexing
Special Microcontroller Features:
ï C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
ï 1000 Erase/Write Cycle Flash Program Memory
Typical
ï Flash Retention: 100 Years Typical
ï Priority Levels for Interrupts
ï 8 x 8 Single-Cycle Hardware Multiplier
ï Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
- 2% stability over VDD and temperature
ï In-Circuit Serial Programmingô (ICSPô) via
Two Pins
ï In-Circuit Debug (ICD) via Two Pins
ï Wide Operating Voltage Range: 2.0V to 5.5V

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