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PIC18F8722 Data Sheet

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发表于 2009-7-25 15:49:56 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
  PIC18F8722 Family Data Sheet (10/2/2008)

Power Management Features:
• Run: CPU On, Peripherals On
• Idle: CPU Off, Peripherals On
• Sleep: CPU Off, Peripherals Off
• Ultra Low 50 nA Input Leakage
• Run mode Currents Down to 25 μA Typical
• Idle mode Currents Down to 6.8 μA Typical
• Sleep mode Current Down to 120 nA Typical
• Timer1 Oscillator: 900 nA, 32 kHz, 2V
• Watchdog Timer: 1.6 μA, 2V Typical
• Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
• Four Crystal modes, up to 40 MHz
• 4x Phase Lock Loop (PLL) – Available for Crystal
and Internal Oscillators
• Internal Oscillator Block:
- Fast wake from Sleep and Idle, 1 μs typical
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock stops
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25 mA
• Three Programmable External Interrupts
• Four Input Change Interrupts
• Enhanced Capture/Compare/PWM (ECCP)
module (40/44-pin devices only):
- One, two or four PWM outputs
- Programmable dead time
- Auto-shutdown and auto-restart
Peripheral Highlights (Continued):
• Up to 2 Capture/Compare/PWM (CCP) modules,
one with Auto-Shutdown (28-pin devices)
• Master Synchronous Serial Port (MSSP) module
Supporting 3-Wire SPI (all 4 modes) and I2C™
Master and Slave modes
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN/J2602
- RS-232 operation using internal oscillator
block (no external crystal required)
• 10-Bit, up to 13-Channel Analog-to-Digital (A/D)
Converter module:
- Conversion available during Sleep
• Dual Analog Comparators with Input Multiplexing
• Programmable 16-Level High/Low-Voltage
Detection (HLVD) module
Special Microcontroller Features:
• C Compiler Optimized Architecture
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: 100 Years Typical
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply 5V In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Wide Operating Voltage Range: 2.0V to 5.5V
• Programmable Brown-out Reset (BOR) with
Software Enable Option


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