dsPIC33FJ06GS102 Data Sheet

enroo_ma

  dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Data Sheet (3/26/2009)


CPU



        Up to 40 MIPS Operation (at 3.0-3.6V)
        16 x 16 Fractional/Integer Hardware Multiply, Single Cycle Execution
        Single-Cycle Multiply and Accumulate
        32-bit by 16-bit Hardware Divider
        C Compiler Optimized Instruction Set
System
        Internal oscillator and Phase-Locked Loop (PLL) with 120 MHz VCO
        On-chip LDO Voltage Regulator
        JTAG Boundary Scan and Flash Memory Program Support
        Fail-Safe Clock Monitor – allows safe shutdown if clock fails
        Watchdog Timer with separate RC oscillator
Power Managed Modes
        Run, Idle and Sleep modes
        Multiple, Switchable Clock Modes for Optimum Performance and Power Management
High-Speed PWM Module Features
        Up to Four PWM Generators with Four to Eight Outputs
        Dead Time for Rising and Falling Edges
        Duty Cycle Resolution of 1.04 ns for Dead-Time, Phase Shift, and Frequency
        Supported PWM modes: Standard Edge-Aligned, True Independent Output, Complementary, Center-Aligned, Push-Pull, Multi-Phase, Variable Phase, Fixed Off-Time, Current Reset, and Current-Limit
        PWMxL, PWMxH Output Pin Swapping
        PWM4H, PWM4L Pins Remappable
        On-the-Fly PWM Frequency, Duty Cycle and Phase Shift Changes
High-Speed Analog Comparator
        Up to Four Analog Comparators
        20 ns response time
        10-bit DAC for each analog comparator
        DACOUT pin to provide DAC output
High-Speed 10-Bit ADC
        10-Bit Resolution
        Up to 12 Input Channels Grouped into Six Conversion Pairs
        4 Msps or  2 Msps Conversion rate
        Independent Trigger Source Section for each Analog Input Conversion Pair
Peripherals
        UART Module with LIN and IrDA® support
        SPI Module with FIFO
        I2C™ Modules with Master and Slave Modes
        Up to 3 16-bit Timer Modules
        Up to 2 Input Capture and 2 Output Compare / PWM
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