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dsPIC30F6010 Datasheet (11/14/2006)
High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
with flexible addressing modes
• 83 base instructions
• 24-bit wide instructions, 16-bit wide data path
• 144 Kbytes on-chip Flash program space
(Instruction words)
• 8 Kbytes of on-chip data RAM
• 4 Kbytes of nonvolatile data EEPROM
• Up to 30 MIPS operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
• 44 interrupt sources:
- 5 external interrupt sources
- 8 user-selectable priority levels for each
interrupt source
- 4 processor trap sources
• 16 x 16-bit working register array
DSP Engine Features:
• Dual data fetch
• Accumulator write-back for DSP operations
• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• All DSP instructions single cycle
• ± 16-bit single-cycle shift
Peripheral Features:
• High current sink/source I/O pins: 25 mA/25 mA
• Timer module with programmable prescaler:
- Five 16-bit timers/counters; optionally pair
16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
• 3-wire SPI modules (supports 4 Frame modes)
• I2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• 2 UART modules with FIFO Buffers
• 2 CAN modules, 2.0B compliant
Motor Control PWM Module Features:
• 8 PWM output channels
- Complementary or Independent Output
modes
- Edge and Center-Aligned modes
• 4 duty cycle generators
• Dedicated time base
• Programmable output polarity
• Dead-time control for Complementary mode
• Manual output control
• Trigger for A/D conversions
Quadrature Encoder Interface Module
Features:
• Phase A, Phase B and Index Pulse input
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Interrupt on position counter rollover/underflow
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